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WM2331
10-bit 30MSPS ADC with PGA and Clamp
DESCRIPTION
The WM2331 is a high speed, 10-bit pipeline analogue-todigital converter (ADC) with on-chip programmable gain amplifier (PGA) and clamp circuit, and internal voltage references. Conversion is controlled by a single clock input. The device has a high bandwidth differential sample and hold input, which gives excellent common-mode noise immunity and low distortion. Alternatively, it can be driven in single ended fashion with an optional voltage clamp for DC restoration that can take its reference from an on-chip 10-bit DAC or an external source. The WM2331 provides internal reference voltages for setting the ADC full-scale range without the requirement for external circuitry. However, it can also accept external references for applications where common or high-precision references are required. A bidirectional 10-bit parallel interface is used both to control the device and to read ADC conversion data. ADC data can be output in unsigned binary or two's complement format. An out-of-range output pin indicates when the input signal is outside the converter's range. The WM2331 operates with independent analogue and digital supplies of 3V to 5.5V and is supplied in a 28-pin TSSOP package.
FEATURES
* * * * * * * * * * * * 10-bit resolution ADC 30MSPS conversion rate Programmable Gain Amplifier (PGA) Built in clamp function (DC restore) with 10-bit DAC Adjustable internal voltage references Wide Input Bandwidth - 150MHz Unsigned Binary or Two's complement output format Programmable via parallel interface Independent analogue and digital supplies, 3V to 5.5V Low power - 92mW typical at 3.0V supplies Powerdown mode to 3mW typical 28-pin TSSOP package
APPLICATIONS
* * * * * * * Composite Video Digitisation Digital Copiers Digital Video Cameras Set Top Box (STB) IF and Baseband Digitisation Medical Imaging High Speed Data Acquisition
BLOCK DIAGRAM
CLAMP CLAMPIN
CLAMP AMPLIFIER
M U X
CLAMP LEVEL DAC
CONTROL REGISTERS
WR
AIN
REFTS
S/H PGA
ADC
Core
INPUT/ OUTPUT BUFFERS
DIO[9:0]
REFBS
OVR
OEB TIMING CONTROL
REFSENSE VREF MODE
ON-CHIP REFERENCE GENERATOR
CLK
DVDD DGND
WM2331
AVDD AGND REFBF REFTF
WOLFSON MICROELECTRONICS LTD www.wolfsonmicro.com
Production Data, July 2001, Rev 1.5. Copyright 2001 Wolfson Microelectronics Ltd.
WM2331 PIN CONFIGURATION
AGND DVDD DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 DIO9 OVR DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AIN VREF REFBS REFBF MODE REFTF REFTS CLAMPIN CLAMP REFSENSE WR OEB CLK
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ORDERING INFORMATION
DEVICE WM2331CDT/V WM2331IDT/V TEMP. RANGE 0 to +70oC -40 to +85oC PACKAGE 28-pin TSSOP 28-pin TSSOP
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME AGND DVDD DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 DIO9 OVR DGND CLK OEB WR REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN AVDD TYPE Ground Supply Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Output Ground Analogue Input Digital Input Digital Input Analogue Input Digital Input Analogue Input Analogue Input/Output Analogue Input/Output Analogue Input Analogue Input/Output Analogue Input/Output Analogue Input/Output Analogue Input Supply Negative Analogue Supply Positive Digital Supply Digital input/output bit 0 (LSB) Digital input/output bit 1 Digital input/output bit 2 Digital input/output bit 3 Digital input/output bit 4 Digital input/output bit 5 Digital input/output bit 6 Digital input/output bit 7 Digital input/output bit 8 Digital input/output bit 9 (MSB) Overrange output (tri-state) Negative Digital Supply Clock input Output enable bar - low to enable DIO[9:0] and OVR Write strobe VREF mode control Clamp control - high to enable clamp amplifier Clamp reference input Top reference sense Top reference force Input mode select Bottom reference force Bottom reference sense Reference voltage Analog Input Positive Analogue Supply DESCRIPTION
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112 and A113, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION Digital supply voltage, DVDD to DGND Analogue supply voltage, AVDD to AGND Supply voltage difference, AVDD to DVDD Ground difference, AGND to DGND Voltage range digital inputs (DIO[9:0], WR, CLAMP, OEB) Voltage range analogue inputs (REFTS, REFBS, REFTF, REFBF, AIN, VREF, REFSENSE, CLK, MODE) Operating temperature range, TA Storage temperature Lead temperature (1.6mm from package body for 10 seconds) WM2331CDT WM2331IDT MIN -0.3V -0.3V -6.5V -0.3V DGND - 0.3V AGND - 0.3V 0C -40C -65C MAX +6.5V +6.5V +6.5V +0.3V DVDD + 0.3V AVDD + 0.3V +70C +85C +150C +300C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Ground Clock frequency Clock duty cycle Operating Free Air Temperature TA WM2331C WM2331I SYMBOL DVDD AVDD DGND,AGND fCLK 5 45 0 -40 50 TEST CONDITIONS MIN 3.0 3.0 NOM 3.0 3.0 0 30 55 70 85 MAX 5.5 5.5 UNIT V V V MHz % C C
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WM2331 ELECTRICAL CHARACTERISTICS
Production Data
Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, PGA gain = 1.0, TA = TMIN to TMAX, unless otherwise stated. PARAMETER DC Accuracy Integral nonlinearity Differential nonlinearity Offset error Gain error Missing codes Analogue Input Signal to AIN pin MODE = AGND Input signal range for unity PGA gain (see Note 1) AIN voltage limits Switched input capacitance Analogue input bandwidth DC leakage current Conversion Characteristics Conversion frequency Pipeline delay Aperture delay Aperture jitter Dynamic Performance Effective number of bits Spurious free dynamic range Total harmonic distortion Signal to noise ratio Signal to noise and distortion ratio PGA Gain range (linear scale) Gain step size (linear scale) Gain error from nominal Clamp Clamp DAC resolution Clamp DAC output voltage Clamp DAC DNL Clamp DAC DNL External clamp reference on CLAMPIN Clamp output voltage error 0.1 -40 REFBF -1 1 AVDD - 0.1 40 10 REFTF 1 bits V LSB LSB V mV 0.5 0.5 3 4 V/V V/V % ENOB SFDR THD SNR SNDR fIN = 3.5MHz fIN = 15MHz fIN = 3.5MHz fIN = 15MHz fIN = 3.5MHz fIN = 15MHz fIN = 3.5MHz fIN = 15MHz fIN = 3.5MHz fIN = 15MHz 51.1 51.2 55 8.2 9.0 7.7 60 48 -58 -47 56 53 56 48 -54.7 bits dB dB dB dB tA fCLK 5 3 4.0 2.0 30 MHz cycles of CLK ns ps rms -3dB amplitude Full-scale input MODE = AVDD / 2, VCMCS fixed MODE = AVDD REFBS VCMCS VREF/2 REFBS AGND 1.2 150 100 REFTS VCMCS + VREF/2 REFTS AVDD V pF MHz A V INL DNL 1.0 0.3 0.4 1.4 2.0 1.0 2.0 3.5 LSB LSB % of FS % of FS SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
No missing codes guaranteed
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Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, PGA gain = 1.0, TA = TMIN to TMAX, unless otherwise stated. PARAMETER Bottom reference voltage applied to REFBS Top reference voltage applied to REFTS Differential reference input (REFTS - REFBS) Reference input common mode (REFTS + REFBS) / 2 Switched input capacitance on REFBS Switched input capacitance on REFTS REFBF output voltage REFTF output voltage Analogue Reference Inputs / Outputs in Centre-Span Mode (MODE=AVDD/2) Reference voltage derived or applied to VREF REFBF output voltage REFTF output voltage Non-AIN side of differential input applied to REFTS and REFBS Differential reference voltage applied (REFTF - REFBF) Reference input common mode (REFTF + REFBF) / 2 Reference input resistance VREF Input / Output specifications Internal 1V reference to VREF Internal 2V reference to VREF External reference applied to VREF pin in centre-span mode Input impedance in centre-span mode REFSENSE = VREF REFSENSE = AGND REFSENSE = AVDD, MODE = AVDD / 2 REFSENSE = AVDD, MODE = AVDD / 2 0.95 1.9 1 18 1.0 2.0 1.05 2.1 2 V V V k AVDD = 3.0V AVDD = 5.0V VCMCS (Note 2) 0.5 1 (AVDD VREF)/2 (AVDD + VREF)/2 AVDD - 0.5 2 V V V V VTB VCMTB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Analogue Reference Inputs / Outputs in Top/Bottom Mode (MODE=AVDD) 0 1 1 0.5 0.6 0.6 (AVDD VTB)/2 (AVDD + VTB)/2 AVDD - 1 AVDD 2 AVDD - 0.5 V V V V pF pF V V
Analogue Reference Inputs / Outputs in Full External Reference Mode (MODE=AGND) (Note 3) 1 1.3 2.0 1.5 2.5 680 2 1.7 3.0 V V V
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Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, PGA gain = 1.0, TA = TMIN to TMAX, unless otherwise stated. PARAMETER Power Supplies MODE = AGND, REFSENSE = AVDD Analogue supply current IAVDD MODE = AVDD/2, REFSENSE = VREF MODE = AVDD, REFSENSE = AVDD Digital supply current Standby power consumption (digital and analogue combined) Input LOW level Input HIGH level Output LOW Output HIGH Notes 1. VCMCS can be applied as a single voltage source to REFTS and REFBS with these two pins connected together. Alternatively the common mode of the input can be set by applying different voltage sources to these two pins, in which case the common mode voltage is effectively the average of these two voltages, VCMCS = (REFTS + REFBS)/2. Digital input and output levels refer to the supply used for the input/output buffer on the relevant pin. CLK and MODE refer to the AVDD supply, all other digital input/output refers to the DVDD supply. In full external reference mode the REFTF and REFTS pins should be shorted together, and the REFBF and REFBS pins should be shorted together. Please refer to device operation examples in the device description section of the datasheet. IDVDD IVDD(STBY) CL = 10pF 31 37 36 6 3 5 45 mA mA mA mA mW SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital Logic Levels (CMOS Levels) VIL VIH VOL VOH (Note 2) (Note 2) IOL = -50A IOH = 50A VDD - 0.2 0.8 x VDD 0.2 0.2 x VDD V V V V
2. 3.
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OEB tOEW WR tDZ DIO[9:0] Output hi - Z tDS Input tDH tDEN hi - Z Output tWRP tWOE
Note: All timing measurements are based on 50% of edge transition
Figure 1 Write Timing
Sample 1 Analogue Input at AIN
Sample 2 Sample 3
tCLK tCL tCH
Sample 5 Sample 4
CLK
tD
Pipeline Delay Digital Output Note: All timing measurements are based on 50% of edge transition Sample 1 Sample 2
Figure 2 Output Timing Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, PGA gain = 1.0, TA = TMIN to TMAX, unless otherwise stated. PARAMETER Clock Clock period Clock high time Clock low time Timing Pipeline delay Clock to data valid Output disable to hi-Z output Output enable to data valid Output disable to write enable Write disable to output enable Write pulse width Input data setup time Input data hold time tD tDZ tDEN tOEW tWOE tWRP tDS tDH 0 0 12 12 15 5 5 3 25 20 20 CLK cycles ns ns ns ns ns ns ns ns tCLK tCH tCL 33 15 15 16.5 16.5 ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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WM2331 TYPICAL SYSTEM PERFORMANCE
Production Data
1 AVDD = DVDD = 3V, fS = 30 MSPS Differential Non-Linearity (LSBs) 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0 128 256 384 512 DIGITAL CODE 640 768 896 1024
Figure 3 Differential Non-Linearity
3 AVDD = DVDD = 3V, fS = 30MSPS Integral Non-Linearity (LSBs) 2 1 0 -1 -2 -3 0 128 256 384 512 DIGITAL CODE 640 768 896 1024
Figure 4 Integral Non-Linearity
0
AVDD = DVDD = 3V, fIN = 3.58MHz, -1dB FS
-20 -40
FFT (dB)
-60 -80 -100 -120 -140 0 3 6 9 12 15
Frequency (MHz)
Figure 5 Fast Fourier Transform (FFT)
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WM2331
DEVICE DESCRIPTION
INTRODUCTION
The WM2331 is a high speed analogue-to-digital converter (ADC) with on-chip analogue preprocessing and reference generation, designed for applications such as composite video digitisation, digital copiers and and high speed data acquisition. The chip architecture consists of: * * * * * * High bandwidth sample and hold input, which can operate in differential or singleended mode Programmable gain amplifier (PGA) Voltage clamp for DC restoration that can take its reference from an on-chip 10-bit DAC or an external source 10-bit, 30MSPS pipeline analogue-to-digital converter (ADC) core On-chip reference generator and reference buffer (external references can also be used for applications where common or high precision references are required) Bidirectional 10-bit parallel interface to read ADC conversion data and control the device. ADC data can be output in unsigned binary or two's complement format. An out-of-range output pin indicates when the input signal is outside the converter's range
ANALOGUE SIGNAL PATH
The WM2331 analogue signal path consists of a DC clamp with a 10-bit clamp level DAC (discussed under `DC Clamp', below), a high-bandwidth sample and hold unit followed by a programmable gain amplifier (PGA) and a fast 10-bit pipelined analogue to digital converter (ADC core).
REFTF VP+ PGA VPVQREFBF Figure 6 Analogue Input Signal Flow Figure 6 shows the signal flow through the sample and hold unit and the PGA to the ADC core, where the process of analogue to digital conversion is performed against the ADC reference voltages, REFTF and REFBF (their generation from internal or external reference sources is described later). VQ+ ADC CORE
AIN REFTS REFBS
+1
SAMPLE -1/2 AND HOLD -1/2
SAMPLE AND HOLD
The analogue input voltage VIN is applied to the AIN pin, either DC coupled, AC coupled, or AC coupled with DC restoration using the WM2331 clamp circuit. The differential sample and hold processes VIN with respect to the voltages applied to the REFTS and REFBS pins, and produces a differential output VP = VP+ - VP- given by:
VP = VIN - VM
where
VM =
REFTS + REFBS 2
For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale input voltage. However, in differential mode (see `ADC Reference Modes', below), REFTS and REFBS can be connected together to operate with AIN as a complementary pair of differential inputs.
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PROGRAMMABLE-GAIN AMPLIFIER
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VP is amplified by the PGA and fed into the ADC as a differential voltage VQ = VQ+ - VQ-
VQ = Gain x VP = Gain x (VIN - VM )
The PGA gain defaults to 1.0 at power-up, but can be programmed from 0.5 to 4.0 in steps of 0.5.
ANALOGUE-TO-DIGITAL CONVERTER
Regardless of the reference configuration, VQ is digitised against ADC Reference Voltages REFTF and REFBF, full scale values of VQ being given by:
VQFS + =
REFTF - REFBF 2
and
ae REFTF - REFBF o VQFS - = -c / 2 e o
Attempts to convert VQ voltages outside the range of VQFS- to VQFS+ are signalled to the application by driving the OVR output pin high. If VQ is less than VQFS-, the ADC output code is 0. If VQ is greater than VQFS+, the output code is 1023.
SIGNAL CHAIN SUMMARY
Combining the above equations and referring back to the input, the positive and negative full-scale voltages at the AIN pin are:
V INFS + = V M +
REFTF - REFBF 2 x Gain
and
V INFS - = V M -
REFTF - REFBF 2 x Gain
Therefore the input signal span is given by:
VINFS + - VINFS - =
REFTF - REFBF Gain
In order to match the ADC input range to the input signal amplitude, REFTF and REFBF should be set such that:
REFTF - REFBF = (V INFS + - V INFS - ) x Gain
ADC REFERENCE MODES
The WM2331 supports three basic modes of reference generation, selected by the voltage applied to the MODE pin. These are summarised and explained in Table 1. In differential, Centre Span and Top/Bottom modes, the internally generated ADC references are intened solely for WM2331 internal use and REFTF and REFBF must not be used as voltage references for any other device in the application.
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MODE FUNCTION COMMENTS On-chip reference generator and reference buffer are not used. VREF can be internally or externally generated. REFTS and REFBS are joined together and connected either to the negative end of the input signal (true differential mode) or to the AIN mid-scale voltage (centre-span mode). On-chip reference generator is not used. Reference buffer centers external reference voltages around AVDD/2.
MODE PIN AGND
Full external
REFTF = REFTS REFBF = REFBS
AVDD + VREF 2 AVDD - VREF 2
AVDD/2
Differential
REFTF = REFTF =
AVDD
Top/Bottom
REFTF = REFBF =
AVDD + (REFTS - REFBS ) 2 AVDD - (REFTS - REFBS ) 2
Table 1 WM2331 Reference Generation Modes
FULL EXTERNAL REFERENCE MODE (MODE = AGND)
When MODE is connected to AGND, the WM2331 operates in full external reference mode. The internal reference buffer is powered down and bypassed, so that the ADC core takes the usersupplied reference voltages at pins REFTS and REFBS (REFTS and REFBS are internally connected to REFTF and REFBF). The mean of REFTF and REFBF must be equal to AVDD/2. Only single-ended input is possible in this mode.
REFTF
AIN REFTS REFBS
+1 -1/2 -1/2
SAMPLE AND HOLD
PGA
ADC CORE
REFBF INTERNAL REFERENCE BUFFER
Figure 7 ADC Reference Generation in Full External Mode The full external mode of operation is useful when the application requires more accurate or lower drift reference voltages than the WM2331 can provide, or when devices need to share common reference voltages for best ADC matching. It also offers the possibility of using REFTS and REFBS as sense lines to drive the REFTF and REFBF lines (Kelvin mode) to eliminate any voltage drops from remote references within the system (see Figure 9). In Kelvin configurations, take care when choosing the external op-amps to ensure that they can drive large capacitive loads without oscillating. Although the on-chip reference generator is not used by the WM2331 in full external mode, its output is available on the VREF pin and can be used by other parts of the system. Note that in addition to the internal connections from REFTS to REFTF and REFBS to REFBF, external wire connections must also be made as shown in Figure 8 to minimise resistance (except in Kelvin mode).
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AVDD
+FS AVDD/2 -FS
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AIN REFTS
REFSENSE
DC SOURCE = AVDD/2 + [(+FS) - (-FS)] * GAIN/2
REFBS
DC SOURCE = AVDD/2 - [(+FS) - (-FS)] * GAIN/2
0.1F
REFTF 10F 0.1F
0.1F REFBF
MODE
Figure 8 Full External Reference Mode (Reference Generator Disabled)
AVDD
+FS AVDD/2 -FS
AIN REFTS
REFSENSE
0.1F +
REFT = AVDD/2 + [(+FS) - (-FS)] * GAIN/2
REFBS REFTF 0.1F 0.1F
0.1F +
REFB = AVDD/2 - [(+FS) - (-FS)] * GAIN/2
10F MODE 0.1F REFBF
Figure 9 Full External Mode with Kelvin connections (Reference Generator Disabled)
DIFFERENTIAL MODE (MODE = AVDD/2)
The WM2331 operates in differential mode when the voltage at the MODE pin is AVDD/2 (midsupply). The ADC reference voltages REFTF and REFBF are generated by the internal reference buffer from VREF. Depending on the connection of the REFSENSE pin, VREF may be supplied by the on-chip reference generator or driven by an external source, as discussed under `On-chip Reference Voltage Generation', below. REFTF and REFBF are centred around AVDD/2 by the internal reference buffer and the voltage difference between them equals VREF.
REFTF = AVDD + VREF 2 AIN REFTS REFBS +1 -1/2 -1/2 REFBF = AVDD - VREF 2
SAMPLE AND HOLD
PGA
ADC CORE
VREF AGND
INTERNAL REFERENCE BUFFER
Figure 10 ADC Reference Generation in Differential Mode This mode is suitable for handling differentially presented inputs, which are applied to the AIN and REFTS/REFBS pins. A special case of differential mode is centre span mode, in which the user applies a single-ended signal to AIN and applies the mid-scale input voltage (VM) to the REFTS and REFBS pins.
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AVDD/2
+FS
WM2331
AIN
-FS
MODE
REFTS
REFBS 0.1F
REFSENSE
REFTF VREF
0.1F
10F
0.1F REFBF
Figure 11 Differential Mode, 1V Reference Span
AVDD/2
+FS VM -FS
AIN REFTS
MODE
DC SOURCE =VM VM + -
REFBS
0.1F
REFTF
0.1F
10F 0.1F REFBF
REFSENSE
Figure 12 Centre Span Mode, 2V Reference Span
TOP/BOTTOM MODE (MODE = AGND)
Top/Bottom mode is enabled by connecting the MODE pin to AVDD. In this mode, the ADC Reference voltages REFTF and REFBF are generated by the internal reference buffer from the externally supplied voltages REFTS and REFBS. Only single-ended input is possible in TOP/BOTTOM Mode.
REFTF = AVDD + (REFTS - REFBS) AIN REFTS REFBS +1 -1/2 -1/2
SAMPLE AND HOLD
PGA
ADC CORE
INTERNAL REFERENCE BUFFER
REFBF = AVDD - (REFTS - REFBS)
Figure 13 ADC Reference Generation in Top/Bottom Mode The voltage difference between REFTS and REFBS should equal the peak-to-peak input signal amplitude times the PGA gain (see `Analogue Signal Path', above). A smaller voltage difference would give rise to out-of-range conditions, whereas a larger one would not fully utilise the ADC resolution. The average of REFTS and REFBS must be the AIN mid-scale voltage, VM. Typically, REFSENSE is tied to AVDD to disable the on-chip reference generator, but the user can also choose to use its output to drive either REFTS or REFBS.
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AVDD
+FS
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AIN
-FS
MODE REFSENSE
REFTS
DC SOURCE = VM + [(FS+) - (FS-)]* GAIN/2
DC SOURCE = VM - [(FS+) - (FS-)]* GAIN/2
REFBS
0.1F
REFTF 10F 0.1F
0.1F REFBF
Figure 14 Top/Bottom Mode (Reference Generator Disabled)
ON-CHIP REFERENCE VOLTAGE GENERATOR
The On-chip Reference Generator (ORG) can provide a reference voltage on the VREF pin that is independent of temperature and supply voltage. External connections to the REFSENSE pin control the ORG's output to VREF, as shown in Table 2. REFSENSE CONNECTION VREF pin AGND External divider junction AVDD ORG OUTPUT TO VREF 1 Volt 2 Volts (1 + RA/RB) Volts - see Figure 15 None (VREF becomes input pin)
Table 2 Controlling the On-chip Reference Generator Connecting REFSENSE to AVDD powers the ORG down, saving power when the ORG function is not required. In differential mode (MODE = AVDD/2), the voltage on VREF determines the ADC reference voltages as follows:
REFTF = REFBF =
AVDD + V REF 2 AVDD - V REF 2
REFTF - REFBF = V REF
When the ORG is enabled, the VREF pin should be decoupled to the circuit board's analogue ground plane close to the WM2331 AGND pin via a 1F tantalum capacitor and a 0.1F ceramic capacitor. The ORG can source currents up to 1mA into external grounded loads when it is not used by the WM2331. Typical buffer load regulation is about 0.5.
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INTERNAL REFERENCE BUFFER MODE = AVDD/2 + - + - RA REFSENSE RB AGND VREF = 1 + (RA/RB) 1F 0.1F tantalum
VBG
Figure 15 ORG Operating with External Divider (for Intermediate Reference Voltages)
DC CLAMP
10-bit DAC CONTROL REGISTER
CLAMPIN CLAMP
+ -
Vclamp
CIN Vin
RIN
AIN
SW1 S/H
Figure 16 Schematic of Clamp Circuitry The WM2331 provides a clamp function for restoring the DC reference level of AC coupled input signals. Figure 17 shows an example of using the clamp to restore the black level of a composite video input AC coupled to AIN. While the clamp pin is held high, the clamp amplifier forces the voltage at AIN to equal the clamp reference voltage, setting the DC voltage at AIN for the video black level.
Line sync Black level
VIDEO AT AIN
CLAMP
Figure 17 Example Waveforms for Line-Clamping to a Video Input Black Level
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Production Data After power up, the clamp reference voltage is the voltage supplied on the CLAMPIN pin. However, it can also be generated by the on-chip 10-bit clamp level DAC by suitably programming the WM2331 clamp and control registers (see Digital Control Registers, below). Clamp design for minimum acquisition time and droop is discussed in Applications Information.
CLAMP DAC OUTPUT VOLTAGE RANGE AND LIMITS
Important: When using the internal clamp DAC in Top/Bottom or Centre Span Mode, the user must ensure that the desired DC clamp level at AIN lies within the voltage range REFBF to REFTF. This is because the clamp DAC voltage is constrained to lie within this range REFBF to REFTF. Specifically: VDAC = REFBF + (REFTF - REFBF) x (0.006 + 0.988x(DAC code)/1024)
DAC codes can range from 0 to 1023. Figure 18 shows the clamp DAC output voltage versus the DAC code.
VDAC VREFTF
VREFBF + 0.006(VREFTF-VREFBF)
VREFBF + 0.987(VREFTF-VREFBF)
VREFBF 0 1023
DAC code
Figure 18 Clamp DAC Output Voltage versus DAC Register Code Value If the desired DC level at AIN does not lie within the range REFTF to REFBF, then either: * * the CLAMPIN pin can be used instead to provide a suitable reference voltage or it may be possible to re-design the application to move the AIN input range into the CLAMP DAC voltage range. This is achieved in both Top/Bottom and Centre Span Modes by shifting both REFTS and REFBS up or down by the voltage through which the AIN input range is to be moved.
DIGITAL CONTROL REGISTERS
The WM2331 contains two clamp registers and a control register for user programming. Binary data can be written into these registers using pins DIO0 to DIO9 and the WR and OEB pins. When writing to a device register, DIO9 and DIO8 select the destination register (see Table 3) and the remaining DIO pins are data bits. ADDRESS DIO[9:8] 00 01 10 11 DESCRIPTION Clamp Reg. 1 Clamp Reg. 2 Control Reg. Reserved DEFAULT (HEX) 00 00 01 READ/ WRITE RW RW RW CLDIS TWOC CLINT PDWN DATA BITS DIO[7:0] DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] DAC[9] DAC[8] PGA[2] PGA[1] PGA[0]
Table 3 Register Map
WRITING TO THE INTERNAL REGISTERS THROUGH THE DIGITAL I/O BUS
Pulling the OEB pin high disables the data and out-of-range indicator (OVR) pins' output drivers, setting the driver outputs to a high impedance state. This allows control register data to be loaded into the WM2331 by presenting it on the DIO0 to DIO9 pins and pulsing the WR pin high then low to latch the data into the chosen control or DAC register. The data is latched into the register on the falling edge of the WR pulse (see Figure 1 for timing details). The new device configuration takes effect as soon as the data is latched into the register.
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WM2331
Figure 19 shows an example register write where the clamp DAC code is set to 199 (hex) by writing to clamp registers 1 and 2 (see `Digital Control Registers', below). Pins DIO0 to DIO7 are driven to the clamp DAC code lower byte (0F hex) and pins DIO8 and DIO9 are both driven to 0 to select clamp register 1 as the data destination. The clamp low-byte data is then loaded into this register by pulsing WR. The top 2 bits of the DAC word are then loaded by driving 01(hex) on pins DIO0 to DIO7 and by driving pin DIO8 to 1 and pin DIO9 to 0 to select clamp register 2 as the data destination. WR is pulsed a second time to latch this second control word into clamp register 2.
NOE
WR
DIO[9:0]
OUTPUT
INPUT 099 Load 99 hex into register 0
INPUT 101 Load 01 hex into register 1
OUTPUT
Figure 19 Example Register Write Cycle to Clamp DAC Register
REGISTER Clamp Register 1 DIO[9:8] = 00
BIT NO 7:0
BIT NAME(S) DAC[7:0]
DEFAULT 0
DESCRIPTION Clamp DAC voltage (DAC[0] = LSB.) DAC[9:0] = 00h: Clamp voltage = REFBF DAC[9:0] = 3Fh: Clamp voltage = REFTF Unused Clamp DAC voltage (DAC[9] = MSB) PGA gain: 000 = 0.5 001 = 1.0 010 = 1.5 011 = 2.0 100 = 2.5 101 = 3.0 110 = 3.5 111 = 4.0 Power down 0 = WM2331 powered up 1 = WM2331 powered down Clamp voltage internal/external 0 = external analogue clamp voltage from CLAMPIN pin. 1 = from on-chip DAC (see Clamp Register) Output format 0 = unsigned binary 1 = two's complement Clamp Amplifier Disable (for power saving) 0 = Enable 1 = Disable Unused
Clamp Register 2 DIO[9:8] = 01 Control Register DIO[9:8] = 10
7:2 1:0 2:0 DAC[9:8] PGA[2:0] 01 001
3
PDWN
0
4
CLINT
0
5
TWOC
0
6
CLDIS
0
7 Table 4 Register Contents
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WM2331
POWER MANAGEMENT
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In power-sensitive applications (such as battery-powered systems) where the WM2331 ADC is not required to convert continuously, power can be saved between conversion intervals by placing the WM2331 into Power Down mode. This is achieved by setting bit 3 (PDWN) of the control register to 1. In Power Down mode, the device typically consumes less than 3mW of power. Power down mode is exited by resetting control register bit 3 to 0. On power up from long periods of power down, the WM2331 typically requires 5ms of wake up time before valid conversion results are available. In systems where the ADC must run continuously, but where the clamp is not required, the supply current can be reduced by approximately 1.2mA by setting the control register bit 6 (CLDIS), which disables the clamp circuit. Similarly, when REFSENSE is tied to AVDD, the reference generator is disabled and supply current reduced by approximately 1.2mA.
DATA OUTPUT FORMAT
While the OEB pin is held low, ADC conversion results are output at the data I/O pins DIO0 (LSB) to DIO9 (MSB). The default output data format is unsigned binary (output codes 0 to 1023). This can be switched to two's complement format (output codes -512 to 511) by setting control register bit 5 (TWOC) to 1.
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WM2331
APPLICATIONS INFORMATION
DRIVING THE CLOCK INPUT
Obtaining good performance from the WM2331 requires care when driving the clock input. Different sections of the Sample-and-Hold and ADC operate while the clock is low or high. The user should ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as possible in which to operate. The CLK pin should also be driven from a low jitter source for best dynamic performance. To maintain low jitter at the CLK input, any clock buffers external to the WM2331 should have fast rising edges. Use a fast logic family such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter. As the CLK input threshold is nominally around AVDD/2, any clock buffers need to have an appropriate supply voltage to drive above and below this level.
DRIVING THE SAMPLE AND HOLD INPUTS
DRIVING THE AIN PIN
Figure 20 shows an equivalent circuit for the WM2331 AIN pin. The load presented to the system at the AIN pin comprises the switched input sampling capacitor, CSample, and various stray capacitances, CP1 and CP2.
AVDD CLK 8pF AIN CP1 CLK AGND + VLAST CP2 = 1.2pF CSample 1.2pF
Figure 20 Equivalent Circuit for Analogue Input Pin AIN The input current pulses required to charge CSample can be time averaged and the switched capacitor circuit modelled as an equivalent resistor
RIN 2 =
1 C S x f CLK
where CS is the sum of CSample and CP2 (see Figure 21). This model can be used to approximate the input loading versus source resistance for high impedance sources.
AVDD CP1 = 8pF AIN IIN + AGND VM = (REFTS + REFBS) /2 RIN2 = 1 / CS fCLK
Figure 21 Equivalent Circuit for the AIN Switched Capacitor Input
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WM2331
AIN INPUT DAMPING
Production Data
The charging current pulses into AIN can make the signal source jump or ring, especially if the source is slightly inductive at high frequencies. Inserting a small series resistor of 20 or less in the input path can damp source ringing (see Figure 22). The resistor can be made larger than 20 if reduced input bandwidth or distortion performance is acceptable.
< 20R AIN VS
Figure 22 Damping Source Ringing Using a Small Resistor
DRIVING THE SAMPLE & HOLD REFERENCE INPUTS
The sample and hold reference inputs (connected to pins REFTS and REFBS) present switchedcapacitor loads similar to the AIN pin, but with smaller capacitors (see Figure 23 below). Note that in Top/Bottom mode, the internal reference buffer is also driven from REFTS and REFBS and the total load on these pins is therefore the parallel combination of the sample and hold circuit and the reference buffer.
AVDD REFTS or REFBS 7pF CP1 CLK AGND Mode = AVDD + VLAST CLK CP2 = 0.6pF 0.6pF
CSample
Internal Reference Buffer
Figure 23 Equivalent Circuit of REFTS and REFBS Sample & Hold Inputs
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WM2331
DRIVING THE INTERNAL REFERENCE BUFFER
DRIVING THE VREF PIN (DIFFERENTIAL MODE)
Figure 24 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin (MODE = AVDD/2 and REFSENSE = AVDD).
AVDD RIN VREF 14K REFSENSE=AVDD, Mode = AVDD/2
AGND
+ -
(AVDD+VREF) / 4
Figure 24 Equivalent Circuit of VREF The input current IREF is given by
I REF =
3V REF - AVDD 4 x R IN
Tolerance on this current is 30 % or greater. The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analogue ground and capable of driving IREF.
DRIVING THE INTERNAL REFERENCE BUFFER (TOP/BOTTOM MODE)
Figure 25 shows the loading on the REFTS and REFBS pins in Top/Bottom mode due to the internal reference buffer. Note that the sample and hold circuit must also be driven via these pins, which adds additional load (see Driving the Sample & Hold Reference Inputs, above).
AVDD REFTS or REFBS RIN 14K Mode = AVDD
AGND AVDD + (REFTS + REFBS) / 4 + -
Figure 25 Equivalent Circuit of Inputs to Internal Reference Buffer The input currents are given by:
I INTS =
and
3REFTS - AVDD - REFBS 4 x R IN
I INBS =
3 REFBS - AVDD - REFTS 4 x R IN
These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving the sample and hold.
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WM2331
DRIVING REFTF AND REFBF (FULL EXTERNAL REFERENCE MODE)
AVDD
Production Data
REFTF
To REFBS (for Kelvin connection)
AGND AVDD 680R
REFBF
To REFTS (for Kelvin connection)
AGND
Figure 26 Equivalent Circuit of REFTF and REFBF Inputs
DESIGNING THE DC CLAMP
Figure 16 (in Device Description) shows the basic operation of the clamp circuit with the analog input AIN coupled via an RC circuit. The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or by programming the on-chip clamp DAC.
INITIAL CLAMP ACQUISITION TIME
Initial acquisition time is defined as the time required to reach the target clamp voltage at AIN when the clamp switch SW1 is closed for the first time (clamp re-acquisition during normal operation is discussed in Steady-state Clamp Voltage Error, below). This time is given by
aeV T ACQ = C IN x RIN x ln c C cV eE
o / / o
where Vc is the difference between the DC level of the input VIN and the target clamp output voltage, VClamp. VE is the difference between the ideal Vc and the actual Vc obtained during the acquisition time. The maximum tolerable error depends on the application requirements. For example, consider clamping an incoming video signal that has a black level near 0.3V to a black level of 1.3V at the WM2331 input. The voltage VC required across the input coupling capacitor is thus 1.3 - 0.3 = 1V. If a 10mV or less clamp voltage error VE will give acceptable system operation, the source resistance Rin is 20 and the coupling capacitor Cin is 1F, then the total clamp pulse duration required to reach this error is: TACQ = 1F x 20 x ln(1/0.01) = 92s (approx.) Note that during continuous operation, the clamping time would typically be much shorter, as the voltage difference wolud be smaller (depending on droop, see next section. Initial acquisition can be performed in two ways: * Pulsing the CLAMP pin as in normal operation. Provided that clamp droop (see below) is negligible, initial acquisition is complete when the total clamped (CLAMP = HIGH) time equals TACQ. Pulling the CLAMP pin high for the required acquisition time before starting normal operation. This method is faster.
*
CLAMP DROOP
The charging currents drawn by the Sample-and-Hold switched capacitor input can charge or discharge CIN, causing the DC voltage at AIN to drift towards VM (the average of REFTS and REFBS) during the time between clamp pulses. This effect is called clamp droop. Voltage droop is a function of the AIN input current to the WM2331, IIN, and the time between clamp intervals, tD:
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WM2331
aeI VDROOP c IN cC e IN
o / x tD / o
(approx.)
Worst case droop between clamping intervals occurs for maximum input bias current. Maximum input current is IINFS, which occurs when the input level is at its maximum or minimum. For example, at 30 MSPS IINFS is approximately 40A for a 2V input range at AIN (see `Driving the Sample and Hold Reference Inputs, above, to calculate IIN). Note that IINFS may vary from this by 30% because of processing variations and voltage dependencies. Designs should allow for this variation. If the time tD between clamping intervals is 63.5s and CIN is 1F then the maximum clamp level droop between clamp pulses is VDROOP = 40A / 1F x 63.5s = 2.5mV (approx.) = 1.25LSB at PGA gain=1, 2V ADC references If this droop is greater than can be tolerated in the application, then increase CIN to slow the droop and hence reduce the voltage change between clamp pulses. If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be significantly worse than calculated above. Avoid using electrolytic and tantalum coupling capacitors as these have higher leakage currents than non-polarised capacitor types. Electrolytic and tantalum capacitors also tend to have higher parasitic inductance, which can cause problems at high input frequencies.
STEADY-STATE CLAMP VOLTAGE ERROR
During the clamp pulse (CLAMP = HIGH), the DC voltage on AIN is refreshed from the clamp voltage. Provided that droop is not excessive, clamping fully reverses the effect of droop. However, using very short clamp pulses with long intervals between pulses (tD) can result in a steady-state voltage difference, VCOS, between the DC voltage at AIN and Vclamp. Figure 27 shows the approximate voltage waveform at AIN resulting from a a large clamp droop during tD and clamp voltage re-acquisition during the clamp pulse time, tC.
Vclamp V VAIN
COS
VDROOP =
V AIN
tc VM
td
Figure 27 Approximate Waveforms at AIN During Droop and Clamping The voltage change at AIN during acquisition has been approximated as a linear charging ramp by assuming that almost all of VCOS appears across RIN, giving a charging current VCOS/RIN (this is a reasonable approximation when VCOS is large enough to be of concern). The voltage change at AIN during clamp acquisition is then
V AIN =
VCOS x t D RIN x C IN
The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state. Equating the droop voltage to the clamp acquisition voltage change gives
VCOS =
RIN x I IN x t D tC
Thus for low offset voltage, keep RIN low, design for low droop and ensure that the ratio tD/tC is not unreasonably large. PD Rev 1.5 July 2001 23
WM2331
REFERENCE DECOUPLING
VREF PIN
Production Data
When the on-chip reference generator is enabled, the VREF pin should be decoupled to the circuit board's analogue ground plane close to the WM2331 AGND pin via a 1F tantalum capacitor and a 0.1F ceramic capacitor.
REFTF AND REFBF PINS
In any mode of operation, the REFTF and REFBF pins should be decoupled as shown in Figure 28 below. Use short board traces between the WM2331 and the capacitors to minimise parasitic inductance.
0.1F REFTF
10F
0.1F REFBF
WM2331
0.1F
Figure 28 Recommended Decoupling for the ADC Reference Pins REFTF and REFBF
SUPPLY DECOUPLING
The analogue (AVDD, AGND) and digital (DVDD, DGND) power supplies to the WM2331 should be separately decoupled for best performance. Each supply needs at least a 10F electrolytic or tantalum capacitor (as a charge reservoir) and a 100nF ceramic type capacitor placed as close as possible to the respective pins (to suppress spikes and supply noise).
DIGITAL OUTPUT LOADING AND CIRCUIT BOARD LAYOUT
The WM2331 outputs are capable of driving rail-to-rail with up to 20pF of load per pin at 30MHz clock and 3V digital supply. Minimising the load on the outputs will improve WM2331 signal-to-noise performance by reducing the switching noise coupling from the WM2331 output buffers to the internal analogue circuits. The output load capacitance can be minimised by buffering the WM2331 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks between the WM2331 and this buffer. Noise levels at the output buffers, which may affect the analogue circuits within WM2331, increase with the digital supply voltage. Where possible, consider using the lowest DVDD that the application can tolerate. Use good layout practices when designing the application PCB to ensure that any off-chip return currents from the WM2331 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any sensitive analogue circuits. The WM2331 should be soldered directly to the PCB for best performance. Socketing the device will degrade performance by adding parasitic socket inductance and capacitance to all pins.
USER TIPS FOR OBTAINING BEST PERFORMANCE FROM THE WM2331
* * * * Choose differential input mode for best distortion performance. Choose a 2V ADC input span for best noise performance. Choose a 1V ADC input span for best distortion performance. Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB traces.
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WM2331
PACKAGE DIMENSIONS
DT: 28 PIN TSSOP (9.7 x 4.4 x 1.0 mm) DM022.A
b
28
e
15
E1
E
GAUGE PLANE 1 14
D 0.25 c A A2 A1 -C0.1 C
SEATING PLANE
L
Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 0.80 0.19 0.09 9.60 4.30 0.45 o 0
Dimensions (mm) NOM --------1.00 --------9.70 0.65 BSC 6.4 BSC 4.40 0.60 ----JEDEC.95, MO-153
MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50 0.75 o 8
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
PD Rev 1.5 July 2001 25
WM2331 IMPORTANT NOTICE
Production Data
Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics Ltd 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom
Tel :: +44 (0)131 667 9386 Fax :: +44 (0)131 667 5176 Email :: sales@wolfsonmicro.com
PD Rev 1.5 July 2001 26

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